Driving circuit of display device

ABSTRACT

A driving circuit of a display device including a TFT (Thin Film Transistor) liquid crystal display device or the like is provided which is capable of decreasing a chip in size and reducing costs of testing by reducing the number of bits even in the case of increased number of bits of digital image data to perform multi-gray shade displaying. The driving circuit of the display device has a gray shade voltage generating circuit adapted to generate a plurality of voltages, gray shade voltage selecting circuits used to select one voltage out of a plurality of voltages supplied from the gray shade voltage generating circuit based on high order bits composed of one or two and more bits counted from the most significant bit of the digital image data and the number of bits of which is smaller than that of the digital image data and to output it, operational amplifiers used to convert an impedance of a voltage outputted from gray shade voltage selecting circuits and voltage adjusting circuits used to induce a voltage rise or a voltage drop in voltages outputted from the operational amplifier based on low order bit of the digital image data excluding its high order bits.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a driving circuit of display devicessuch as TFT (Thin Film Transistor) liquid crystal display devices andthe like and more particularly to the driving circuit used to displaydevices, which is capable of displaying multi-shades of gray.

2. Description of the Related Art

Development of a liquid crystal display device is recently prevailingwhich also stimulates further development of a driving circuit used forthe liquid crystal device.

A driving circuit of the display device for 6-bit 240 output digitalimage data is described in Society for Information Display (SID)International Symposium digest of technical papers (S. Saito and K.Kitagawa of NEC Corp. Kanagawa, Japan, Vol. XXVI, pp. 257-260, Figure 1,1995). FIG. 11 is a schematic block diagram showing the conventionaldriving circuit used for display devices described in the aboveliterature.

The conventional driving circuit is provided with a 80-bit shiftregister circuit 51 into which a switching signal R/L and a clock signalCLK are inputted, both of which are adapted to switch aninputting/outputting direction of a start pulse signal SP. The startpulse SP is inputted into either of a terminal SPR or a terminal SPL inaccordance with the switching signal R/L and is outputted from otherterminal to an adjacent driving circuit. To this shift register 51 isconnected to a data register circuit 52 in which data for 6-bit 3outputs including D00 to D05, D10 to D15 and D20 to D25 is sequentiallystored. To this data register circuit is connected a data latch circuit53 into which a latch circuit STB is inputted. A gray shade voltagegenerating circuit 56 is provided, which is used to divided gray shadevoltages including 9 voltage values from V0 to V8 and to output one grayshade voltage. Moreover, a gray shade voltage selecting circuit 54 isprovided which is used to select one gray shade voltage out of 64 grayshade voltages outputted from the gray shade voltage generating circuit56 based on image data transferred from the data latch circuit 53. Thegray shade voltage selecting circuit 54 has 64 ROM decoders.Furthermore, an amplifier 55 in which an operational amplifier is builttherein is also mounted, which is used to perform an impedanceconversion of signals outputted from the gray shade voltage selectingcircuit 54.

In the gray shade voltage generating circuit 56, the gray shade voltagesof 9 values inputted from outside are divided to generate the gray shadevoltages of 64 values. Such a voltage dividing method is generallycalled a “resistance string method”.

Moreover, the gray shade selecting circuit 54 is composed of, forexample, an enhancement mode transistor and a depletion mode transistor.

In the conventional driving circuit having such configurations asdescribed above, when the start pulse SP is inputted into the shiftregister circuit 51, data for 6-bit 3 outputs including D00 to D05, D10to D15 and D20 to D25 is sequentially stored.

Next, when the latch signal STB is inputted into the data latch circuit53, all digital image data that had been stored in the data registercircuit 52 is transferred to the data latch circuit 53 and storedtherein.

From the gray shade voltage generating circuit 56 is supplied gray shadevoltages of 64 values to the gray shade voltage selecting circuit 54and, when the digital image data is transferred to the data latchcircuit 53, one gray shade voltage is selected out of the gray shadevoltage of 64 values based on the digital image data and is outputted.

The voltage outputted from the gray shade voltage selecting circuit 54,after its impedance is converted by the operational amplifier embeddedin the amplifier 55, is applied to liquid crystals implemented in theliquid crystal display device.

However, in the conventional driving circuit described above, though itis possible to generate 64 (6-bit) gray shade voltages without anyproblem, if gray shades exceeding 64 have to be generated, there arefollowing various problems to be solved.

That is, according to a conventional resistance string method, as thenumber of shades of gray increases, a size of a chip for the gray shadeselecting circuit 54 significantly increases. For example, in the caseof a driver used for 65 shades of gray, the gray shade voltage selectingcircuit must have 64 pieces of ROM decoders per one output while, in thecase of a driver used for 256 shades of gray, the gray shade voltageselecting circuit must have 256 pieces of ROM decoders (i.e., 4 timeslarger than 64 ROM decoders) per one output. Therefore, if these driversmust be implemented on a semiconductor integrated circuit, a device areamust be 4 times as large as that for 64 shades of gray, thus causing asignificant increase in the size of the chip.

Also, in the case of the driving circuit used for 64 shades of gray,since the gray shade voltage selecting circuit 54 has 64 ROM decoders,checking of operations of all these 64 decoders is required accordingly.In the case of the driving circuit used for 256 shades of gray, it isalso necessary to check operations of all 256 decoders as well. Becauseof this, time required for testing is increased by four times, thusincreasing test time required in an inspection process in asemiconductor circuit production and resulting in increased costs fortesting.

SUMMARY OF THE INVENTION

In view of the above, it is an object of the present invention toprovide a driving circuit of a display device which is capable ofdecreasing a chip in a size and reducing cots for testing in productionprocesses by reducing the number of devices even if the number of bitsof digital image data is increased for displaying multi-shades of gray.

According to a first aspect of the present invention, there is providedthe driving circuit of the display device for displaying a plurality ofgray shades based on inputted digital image data including:

-   -   gray shade voltage generating means for generating a plurality        of voltages;    -   gray shade voltage selecting means for selecting one voltage out        of a plurality of voltages supplied from the gray shade voltage        generating means based on high order bits composed of one or two        and more bits counted from the most significant bit of the        digital image data and the number of bits of which is smaller        than that of the digital image data, and for outputting the        voltage;    -   an operational amplifier used to convert an impedance of a        voltage outputted from the gray shade voltage selecting means;        and    -   voltage adjusting means for inducing a voltage rise or a voltage        drop of a voltage outputted from the operational amplifier based        on low order bits of the digital image data excluding the high        order bits.

In the foregoing, a preferable mode is one wherein the voltage adjustingmeans includes a resistor connected to an output terminal of theoperational amplifier, an active device connected to the resistor andcontrolling means for controlling operations of the active device basedon the low order bits.

Also, a preferable mode is one wherein the active device has a firsttransistor, a drain of which is connected to the resistor, a source ofwhich supply power is applied to and a second transistor a drain ofwhich is connected to the resistor, a source of which is connected to aground and a gate voltage of which is controlled by the controllingmeans.

Also, a preferable mode is one wherein the resistor is composed of ananalog switch.

Also, a preferable mode is one wherein the gray shade voltage selectingmeans, when values between adjacent gray shade voltages are not equal,is used to select one voltage out of a plurality of voltages fed by thegray shade voltage generating means based on all bits of the digitalimage data and wherein the voltage adjusting means is used to output avoltage, as it is, outputted from the operational amplifier.

According to a second aspect of the present invention, there is providedthe driving circuit of the display device for displaying a plurality ofgray shades based on inputted digital image data including:

-   -   gray shade voltage generating means for generating a plurality        of voltages;    -   gray shade voltage selecting means for selecting two or more        voltages out of a plurality of voltages supplied from the gray        shade voltage generating means based on high order bits composed        of one or two and more bits counting from the most significant        bit of the digital image data and the number of bits of which is        smaller than that of the digital image data;    -   dividing means for dividing two or more voltages outputted from        the gray shade voltage selecting means and for one divided        voltage based on low order bits of the digital image data        excluding the high order bits; and    -   an operational amplifier used to convert an impedance of a        voltage outputted from the dividing means.

In the foregoing, it is preferable that the gray shade voltage selectingmeans, when values between adjacent gray shade voltages are not equal,is used to select one voltage out of a plurality of voltages suppliedfrom the gray shade voltage generating means based on all bits of thedigital image data and to output the voltage.

Also, it is preferable that the gray shade voltage generating means isprovided with two or more input terminals to which an voltage isinputted from outside and with dividing means used to divide voltagesinputted into the input terminals into many voltages.

Also, it is preferable that a voltage outputted from the gray shadevoltage generating means is a positive polarity voltage or a negativepolarity voltage.

Furthermore, it is preferable that, when the number of bits of thedigital image data is N, the high order bits are composed of (N−m) bitscounted from the most significant bit of the digital image data and thelow order bits are composed of m bits counted from the least significantbit of the digital image data.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the presentinvention will be more apparent from the following description taken inconjunction with the accompanying drawings in which:

FIG. 1 is a schematic block diagram showing a driving circuit accordingto a first embodiment of the present invention;

FIG. 2 is a schematic circuit diagram of a gray shade voltage generatingcircuit in the driving circuit of the first embodiment;

FIG. 3A is a schematic circuit diagram of a first gray shade voltageselecting circuit and FIG. 3B is a schematic circuit diagram of a secondgray shade voltage selecting circuit;

FIG. 4 is a schematic circuit diagram of switches for gray shade voltageselecting circuits;

FIG. 5 is a schematic block diagram showing first and second outputcircuits shown in FIG. 1;

FIG. 6 is a time chart showing operations of a first output circuit 9according to the first embodiment;

FIG. 7 is a graph showing a relationship between output voltage andtransmission rate.

FIG. 8A is a graph showing a relationship between the number of grayshades and an output voltage at the time when a white color or blackcolor is displayed on the liquid crystal display device in which thenumber of shades of gray is plotted as abscissa and the output voltageas ordinate and

FIG. 8B is a graph showing a relationship between the number of grayshades and an output voltage at the time when an intermediate color(gray) is displayed on the liquid crystal display device in which thenumber of shades of gray is plotted as abscissa and the output voltageas ordinate.

FIG. 9 is a schematic block diagram of a driving circuit according to asecond embodiment;

FIG. 10 is a schematic block diagram of a driving circuit according to athird embodiment; and

FIG. 11 is a schematic block diagram showing a conventional drivingcircuit used for a display device.

FIG. 12 is a schematic block diagram of an analog switch provided ingray shade voltage selecting circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Best modes of carrying out the present invention will be described infurther detail using various embodiments with reference to theaccompanying drawings.

First Embodiment

In a first embodiment, 8-bit digital image data is inputted. FIG. 1 is aschematic block diagram showing a diving circuit according to the firstembodiment of the present invention.

The driving circuit of the first embodiment is provided with a shiftregister circuit 1 into which a start pulse SP and a clock signal CLKare inputted and which is used to shift contents of the register insynchronization with the clock signal CLK. The driving circuit also hasa data buffer circuit 4 used to temporarily store digital image data D00to D07, D10 to D17 and D20 and D27 and a data register circuit 2 used tosave these data. The data register circuit 2 is provided with 16registers 2a. Moreover, the driving circuit has a data latch circuit 3used to latch the digital image data and a latch control circuit 5 usedto control operations of the data latch circuit 3. Into this latchcontrol circuit 5 is inputted a latch control signal STB and a polaritysignal POL.

In FIG. 1, signal lines extending from the data buffer circuit 4 and notbeing connected to the data register circuit 2 are connected to a dataregister circuit (not shown).

The driving circuit is further provided with a gray shade voltagegenerating circuit 6 used to divide gray shade voltages including 10voltage values from V0 to V9 and to input 128 gray shade voltages havingeither of positive polarity or negative polarity. It is also providedwith a first gray shade voltage selecting circuit 7 and a second grayshade voltage selecting circuit 8 which are adapted to select one grayshade voltage out of 128 gray shade voltage outputted from the grayshade voltage generating circuit 6 based on high order 7 bits of thedigital image data transferred from the data latch circuit 3. Into thefirst gray shade voltage selecting circuit 7 is inputted a positive grayshade voltage and into the second gray shade selecting circuit 8 isinputted a negative gray shade voltage. Furthermore, the driving circuitis provided with a first output circuit 9 and a second output circuit 10in which operational amplifiers are built in and an impedance of asignal outputted from the first gray shade voltage selecting circuit 8is converted. Between the first gray shade voltage circuit 8 and thefirst output circuit 9/second output circuit 10 are analog switched 60,61 used to select connections between them. The latch control signal STBand polarity signal POL are inputted into the first output circuit 9 andsecond output circuit 10 from the latch control circuit 5 and the leastsignificant bit of the digital image data is inputted from the datalatch circuit 3.

FIG. 2 is a schematic circuit diagram of the gray shade voltagegenerating circuit 6. As shown in FIG. 2, the gray shade voltagegenerating circuit 6 has 127 resistors +R1, +R2, +R3, . . . , +R125,+R126, +R127 connected in serial and 127 resistors −R1, −R2, −R3, . . ., −R125, −R126, −R127 connected in serial. A positive gray shade supplyvoltage VX0 is inputted to an end terminal of the resistor +R1 side anda positive gray shade voltage +V0 is outputted from this end terminal. Apositive gray shade supply voltage VX4 is inputted to an end terminal ofthe resistor +R127 side and a positive gray shade voltage +V254 isoutputted from this end terminal. Moreover, gray shade voltages from +V2to +V252 are outputted from each connection point disposed betweenresistors, starting from the resistor +R1 side. The gray shade voltagesfrom VX1 to VX3 are inputted to each connection point arbitrarilydisposed between the resistor +R1 and the resistor +R127. A negativegray shade voltage VX5 is inputted to an end terminal of the resistor−R127 and the gray shade voltage −V254 is outputted from this endterminal. A negative gray shade voltage VX9 is inputted to an endterminal of a resistor −R1 side and a gray shade voltage −V0 isoutputted from this end terminal. Negative gray shade voltages from −V2to −V252 are outputted from each connection point between resistors,starting from the resistor −R1 side. The gray shade voltages from VX6 toVX8 are inputted to each connection point arbitrarily disposed betweenthe resistor −R1 and the resistor −R127.

In the gray shade voltage generating circuit 6, the gray shade supplyvoltages from VX0 to VX4 is divided through the resistors from +R1 to+R127 to generate 128 positive gray shade voltages from +V0 to +V254.Similarly, the gray shade supply voltages from VX5 to VX9 is dividedthrough the resistors from −R1 to −R127 to generate 128 negative grayshade voltages from −V0 to −V254. Therefore, the gray shades of 128×2values are generated. Positive gray shade voltages of 128 values aresupplied to the first gray shade voltage selecting circuit 7 andnegative gray shade voltages of 128 values are supplied to the secondgray shade voltage selecting circuit 8.

FIG. 3A is a schematic circuit diagram of a first gray shade voltageselecting circuit and FIG. 3B is a schematic circuit diagram of a secondgray shade voltage selecting circuit. To an output terminal of the firstgray shade voltage selecting circuit 7 is, in parallel, connected 128switches from +SW0 to SW127. To each of switches from +SW0 to +SW127 isinputted each of gray shade voltage from +V0 to V254. One switch out ofthese switches +SW0 to SW127 is turned ON in accordance with high order7 bits of the digital image data and one gray shade voltage is selectedand outputted. That is, one gray shade value out of 128 gray shadevalues is selected and outputted. To an output terminal of the secondgray shade voltage selecting circuit 8 are connected 128 switches fromSW0 to SW127 in parallel. To each of the switches from SW0 to SW127 isinputted gray shade voltages −V0 to −V254. One of switches SW0 to SW127is turned ON in accordance with high order 7 bits of the digital imagedata and one gray shade voltage is selected and outputted, i.e., onegray shade voltage out of 128 gray shade voltages is selected andoutputted.

FIG. 4 is a schematic circuit diagram of switches for gray shade voltageselecting circuits. The gray shade voltage selecting circuit is providedwith transistors composed of, for example, 128 lines and 14 columnsarranged in an array form. In FIG. 4, a transistor with an ellipse drawnin its channel portion is a depletion mode transistor and one withoutthe ellipse drawn is an enhancement mode transistor. For example, in the14th column from the left in FIG. 4, the depletion mode transistor andthe enhancement mode transistor are alternately arranged in order and,in the 13th column, with each depletion mode transistor exchanged witheach enhancement mode transistor compared with those in the 14th column,they are alternately arranged in order. Moreover, in the 12th columnfrom the left in FIG. 4, two consecutive depletion mode transistors andtwo consecutive enhancement mode transistors are alternately arranged inorder and, in the 11th column, with two consecutive depletion modetransistors exchanged with two consecutive enhancement transistorscompared with those in the 12th column, they are alternately arranged inorder. In the 10th column from the left, four consecutive depletion modetransistors and four consecutive enhancement mode transistors arealternately arranged in order. In the 8th column, eight consecutivedepletion mode transistors and eight consecutive enhancement modetransistors are alternately arranged. In the 6th column, sixteenconsecutive depletion mode transistors and sixteen consecutiveenhancement mode transistors are alternately arranged as well. In the4th column, thirty-two consecutive depletion mode transistors andthirty-two consecutive enhancement mode transistors are alternatelyarranged. In the 2nd column, sixty-four consecutive depletion modetransistors and sixty-four consecutive enhancement mode transistors arealternately arranged. In each column with an odd number, each of thedepletion mode transistors is replaced with each of the enhancement modetransistors compared with each column with an even number.

Each gate of transistors mounted in columns with an even number isconnected to inverters IV1 to IV7 and is further connected through theseinverters IV1 to IV7 to each gate of transistors mounted in columns withan odd number and to data latch circuit 3. One bit digital image data isinputted to each of 7 pairs of even number and odd number columns.

By constructing switches of the gray shade voltage selecting circuitusing such ROM-type decoders, a chip size can be made very small.

Moreover, when a voltage of higher voltage side relative to liquidcrystal common voltages (i.e., potential of common electrode) isoutputted, the ROM-type decoder is composed of P-channel enhancementmode transistors and P-channel depletion mode transistors and, when avoltage of lower voltage side relative to the liquid crystal commonvoltages (i.e., potential of common electrode) is outputted, theROM-type decoder is composed of N-channel enhancement mode transistorsand N-channel depletion mode transistors. In this embodiment, the formercorresponds to the first gray shade voltage selecting circuit 7 and thelatter corresponds to the second gray shade voltage selecting circuit 8.

FIG. 5 is a schematic block diagram showing first and second outputcircuits shown in FIG. 1. Each of the output circuits is provided withan operational amplifier 11 used to amplify an output signal fed fromthe gray shade voltage selecting circuit and to convert its impedance.Between the operational amplifier 11 and an output terminal connected tothe display device is connected a resistor 12 including an analog switchor the like. Between the resistor 12 and the output terminal areconnected transistors M1 and M2 drains of which are connected to eachother. A source of the transistor M1 is connected to a terminal ofsupply voltage VDD and a source of the transistor M2 is connected to aground GND. Gates of the transistors M1 and M2 are connected to an LSBcontrol circuit 13. To the LSB control circuit 13 are inputted the leastsignificant bit (1 bit) of the digital image data and polarity signalPOL and latch signal STB. That is, an output offset control circuit 14is composed of transistors M1 and M2 and of the LSB control circuit 13.

The output circuit having configurations described above is controlledby the least significant bit of the digital image data. A voltageselected based on high order 7 bits of the digital image data isoutputted as it is or after an offset voltage is added.

The transistors M1 and M2 are switched ON or OFF by the LSB controlcircuit 13 based on the least significant bit of the digital image data.When both of the transistors M1 and M2 are in an OFF state, though theoutput voltage from the operational amplifier 11 is applied, as it is,to a display device, when either of the transistors M1 or M2 is in an ONstate, a steady state current of Im is generated which flows through thetransistor M1 or M2 being in the ON state. If a resistance value of theresistor 12 including analog switches or the like is Rm, an offsetvoltage of ΔV=Im×Rm is generated due to a voltage drop and this voltageis added to the output voltage from the operational amplifier 11 and thetotal voltage is applied to the display device from the output terminal.Moreover, the steady state current Im and the analog resistance Rm areset so that the voltage ΔV is one gray shade in a halftone region (i.e.,during a region II in FIG. 7).

Operations of the driving circuit according to the first embodiment aredescribed below (with reference to FIG. 1).

When the start pulse signal SP is inputted into the shift registercircuit 1, 8-bit three outputs of digital image data including D00 toD07, D10 to D17 and D20 to D27 are sequentially stored in the dataregister circuit 2.

Next, when the latch signal STB is inputted into the data latch circuit3 from the latch control circuit 5, all of the digital image data storedwithin the data register circuit 2 is transferred to the data latchcircuit 3 and stored therein.

Moreover, 128 gray shade voltages obtainable by dividing 10 gray shadesupply voltage VX0 to VX9 are supplied from the gray shade generatingcircuit 6 to the first gray shade selecting circuit 7 and the secondgray shade selecting circuit 8. When the digital image data istransferred to the data latch circuit 3, one gray shade is selected,based on high order 7 bits of the digital image data, by the first grayshade voltage selecting circuit 7 from positive polarity 128 gray shadevalues. Similarly, one gray shade value is selected by the second grayshade voltage selecting circuit 8 from negative polarity 128 gray shadevalues.

If the TFT (Thin Film Transistor) liquid crystal display device isdriven in dot reverse, when the polarity signal POL is 0 (low), anegative polarity voltage is inputted from the second gray shade voltageselecting circuit 8 to the first output circuit 9 and a positivepolarity voltage is inputted from the first gray shade selecting circuit7 to the second output circuit 10. On the other hand, if the polaritysignal POL is 1 (high), a positive polarity voltage is inputted from thefirst gray shade voltage selecting circuit 7 to the first output circuit9 and a negative polarity voltage is inputted to the second outputcircuit 10 from the second gray shade selecting circuit 8.

FIG. 6 is a time chart showing operations of the first output circuit 9according to the first embodiment. In the first output circuit 9, if theleast significant bit LSB is 0 (low), both of the transistors M1 and M2are turned OFF regardless of the polarity signal POL. At this point, thevoltage drop in the resistor 12 including analog switches or the likedoes not occur because currents do not flow constantly, an outputvoltage supplied from the operational amplifier 11, as it is, is appliedto the display device from the output terminal.

On the other hand, if the least significant bit LSB is 1 (high), by thepolarity signal POL, either of the transistor M1 or M2 is turned ON.That is, if the polarity signal POL is 0 (low), a negative polarityvoltage from the second gray shade selecting circuit 8 is applied to theoperational amplifier 11 of the first output circuit 9, the transistorM1 is turned ON and the transistor M2 remains OFF. Therefore, a steadystate current Im1 flows through the transistor M1 and, since the supplyvoltage VDD is supplied to a source of the transistor M1, a voltage riseof ΔVn=Im1×Rm occurs at the resistor 12.

Then, if the polarity signal POL becomes 1 (high) while the leastsignificant bit LSB remains high, a positive polarity voltage fed by thefirst gray shade selecting circuit 7 is applied to the operationalamplifier 11 of the first output circuit 9 and, at the same time, thetransistor M1 is turned OFF while the transistor M2 is turned ON.Therefore, since the steady state current Im2 flows through thetransistor M2 and the source of the transistor M2 is connected to aground GND, a voltage drop ΔVp=Im2×Rm occurs at the resistor 12.

The operation of the first output circuit 9 is described above, whilethe operation of the second output circuit 10 is the reverse of that ofthe first output circuit 9. For example, if the polarity signal POL is 0(low) when the least significant bit LBS is 1 (high), a positivepolarity voltage fed from the first gray shade voltage selecting circuit7 is applied to the operational amplifier 11 of the second outputcircuit 10 and, at the same time, the transistor M2 is turned ON whilethe transistor M1 remains OFF. Therefore, since the steady state currentIm2 flows through the transistor M2 and the source of the transistor M2is connected to a ground GND, a voltage drop ΔVp=Im2×Rm occurs at theresistor 12.

Thus, an impedance of a voltage outputted from the first gray shadevoltage selecting circuit 7 and the second gray shade voltage selectingcircuit 8 is converted by the operational amplifier 11 built in theoutput circuits 9 and 10 and is applied to the liquid crystal within theliquid crystal display device.

Accordingly, when the polarity signal POL is 0 (low), a negativepolarity voltage is outputted from the first output circuit 9 and whenthe polarity signal POL is 1 (high), a positive polarity voltage isoutputted from the same. On the other hand, a positive polarity voltageis outputted from the second output circuit 10 when the polarity signalPOL is 0 (low), while a negative polarity voltage is outputted from thesame when the polarity signal POL is 1 (high). The following table showsa relationship between the digital image data and output voltage.

TABLE 1 Number of gray Positive Negative shades Image data polaritypolarity  0 00 +V0 −V0  1 01 +V0 − ΔV_(P) −V0 + ΔV_(N)  2 02 +V2 −V2  303 +V2 − ΔV_(P) −V2 + ΔV_(N) . . . . . . . . . . . . 126 7E +V126 −V126127 7F +V126 − ΔV_(P) −V126 + ΔV_(N) 128 80 +V128 −V128 129 81 +V128 −ΔV_(P) −V128 + ΔV_(N) . . . . . . . . . . . . 252 FC +V252 −V252 253 FD+V252 − ΔV_(P) −V252 + ΔV_(N) 254 FE +V254 −V254 255 FF +V254 − ΔV_(P)−V254 + ΔV_(N)

FIG. 7 is a graph showing a relationship between output voltage andtransmission rate in which the output voltage is plotted as abscissa andthe transmission rate as ordinate. FIG. 8A is a graph showing arelationship between the number of gray shades and an output voltage atthe time when a white color or black color is displayed on the liquidcrystal display device in which the number of shades of gray is plottedas abscissa and the output voltage as ordinate. FIG. 8B is a graphshowing a relationship between the number of gray shades and an outputvoltage at the time when an intermediate color (gray) is displayed onthe liquid crystal display device in which the number of shades of grayis plotted as abscissa and the output voltage as ordinate.

As shown in FIG. 7, the transmission rate decreases as the outputvoltage increases. As shown in Table 1, FIG. 8A and FIG. 8B, if thenumber of shades of gray is different, the output voltage is different.Therefore, as described in this embodiment, by dividing the digitalimage data into high order 7 bits and low order 1 bit and by applyingthe resistance string method to the high order 7 bits of the digitalimage data and applying an offset method to low order 1 bit of thedigital image data, multi-gray shade display is made possible.

Thus, according to this embodiment, since the resistance string methodis used for the high order 7 bits of the digital image data and theoffset method for the low order 1 bit of the digital image data, thenumber of devices within the gray shade voltage selecting circuits 7 and8 to be controlled by the high order 7 bits of the digital image datacan be as small as 1792 (2×7×128). The number of devices of the LSBcontrol circuit 13 to be controlled by the low order 1 bit can be assmall as 30. On the other hand, in the conventional 8-bit resistancestring method, 4096 (2×8×256) devices per one output are required forthe gray shade voltage selecting circuit. The number of devices withinthe gray shade voltage selecting circuit can be decreased by 2304 andcan be decreased by 2274 as a total when the number of devices of theLSB control circuits are taken into account. This enables the number ofdevices to be greatly decreased and the chip to be decreased in size.

Furthermore, in the conventional resistance string method, since it isnecessary to check operations of 256 ROM decoders, 256 time functionaltests are required. In contrast, according to this embodiment, since theresistance string method is applied to the high order 7 bits and theoffset method to the low order 1 bit and, therefore, operations of 128ROM decoders within the gray shade voltage selecting circuit must bechecked, thus requiring the 128 time functional tests. In the case ofthe offset method applied to the low order 1 bit, since three timechecking is necessary, at least 131 time functional tests must beperformed. Thus, according to this embodiment, since the number of timesof the testing can be much decreased, a great reduction in the costs ofthe testing is made possible.

Moreover, not only analog switches but also other diffusion resistors orpolycrystal silicon resistors may be used for the resistor 12 in theembodiment.

Second Embodiment

FIG. 9 is a schematic block diagram of a driving circuit according to asecond embodiment. Some reference numbers in FIG. 9 of the secondembodiment designate corresponding parts in FIG. 1 of the firstembodiment and their detailed descriptions are omitted.

According to the second embodiment, the driving circuit is providedadditionally with an operational amplifier 21 connected to the positivepolarity gray shade voltage selecting circuit 7 and an operationalamplifier 22 connected to the negative polarity gray shade voltageselecting circuit 8. Moreover, to output terminals of the operationalamplifiers 21 and 22 are connected output offset control circuits 23 and24 through analog switched 60, 61. These output offset control circuits23 and 24 have the same configurations as the output offset circuit 14of the first embodiment. To these output offset control circuits 23 and24 are connected output terminals to be connected to the display devicesuch as TFT liquid crystal display panels or the like.

According to the second embodiment, analog switches 60, 61 used to makea switching between the first gray shade voltage selecting circuit 7 andthe second gray shade voltage selecting circuit 8 and between the outputoffset control circuit 23 and 24 have the same function as the resistor12 mounted within the output circuit of the first embodiment. That is,gray shades are adjusted by using a voltage rise or drop generated bythe analog switches 60, 61. Because of this, in the first embodiment,any component that can be a resistance component may be the resistor 12,however, in the second embodiment, unless the component is an analogswitch, the liquid crystal display device is not driven in dot reverse.

In the first embodiment, to produce an offset in the output voltage, anexclusive diffusion resistor or polycrystal silicon resistor isrequired. In contrast, in the second embodiment, since analog switchesare connected to output terminals of the operational amplifiers 21 and22, such exclusive resistors are not necessary, thus enabling circuitsto be more simplified compared with the case of the first embodiment.

Third Embodiment

According to a third embodiment, a driving circuit for line reversion isprovided. FIG. 10 is a schematic block diagram of a driving circuitaccording to the third embodiment. Same reference numbers in FIG. 9 ofthe second embodiment designate corresponding parts in FIG. 1 of thefirst embodiment and their detailed descriptions are omitted.

According to the third embodiment, the driving circuit is provided witha data latch circuit 36 adapted to latch digital image data and a latchcontrol circuit 37 adapted to control operations of the data latchcircuit 36. Since the driving circuit of this embodiment is used for theline reversion which does not require a polarity signal, to this latchcontrol circuit 37 is inputted a latch signal STB only.

It also has a gray shade voltage generating circuit 35 used to dividegray shade voltages including 9 voltage values from V0 to V8 into 128shades of gray having either of the positive or negative polarity and tooutput them. Though configurations of the gray shade voltage generatingcircuit 35 are the same as those shown in FIG. 2 of the firstembodiment, according to this embodiment, a resistance string havingeither of positive or negative polarity is mounted thereon. From thisgray shade voltage generating circuit 35 are generated gray shadevoltages of 128 values.

Moreover, the driving circuit of this embodiment is provided with afirst gray shade voltage selecting circuit 31 and a second gray shadevoltage selecting circuit 32 adapted to select one gray shade voltageout of 128 gray shade voltages outputted from the gray shade voltagegenerating circuit 35 based on the digital image data transferred to thedata latch circuit 36. The first gray shade voltage selecting circuit 32are provided with transfer-gate type analog switches composed ofp-channel transistors and n-channel transistors as illustrated in FIG.12. It also has a first output circuit 33 used to convert an impedanceof a voltage outputted from the first gray shade selecting circuit 31and a second output circuit 34 used to convert an impedance of a voltageoutputted from the second gray shade selecting circuit 32.Configurations of the first output circuit 33 and the second outputcircuit 34 are the same as the output circuit in the first embodiment.However, to the LSB (Least Significant Bit) control circuit built inthese circuits are inputted the least significant bit LSB of the digitalimage data and the latch signal STB only.

Thus, according to the third embodiment, both polarities can be selectedby using the gray shade voltage selecting circuits 31 and 32 regardlessof positive or negative polarities, the FTF liquid crystal panel isdriven in line reverse.

Moreover, in the first to third embodiments, both the resistance stringmethod and the method in which an offset is produced in output voltagesare employed in all output voltages. However, as shown in FIG. 8A,during the areas I and III, it is difficult to obtain sufficient effectsby such offset produced. Therefore, preferably, the 8-bit resistancestring method only is applied during the areas I and III, while both theresistance string method and the method in which the offset is producedin output voltages are applied during the area II. That is, only the8-bit resistance string method is applied during gray shades from 0 to31 shades of gray (area I) and during gray shades from 224 to 255 shadesof gray (area III). Moreover, during gray shades from 32 to 223 shadesof gray (area II), both the 7-bit resistance string method and themethod in which the offset is produced based on the least significantbit are employed.

Thus, the output voltage can be adjusted by setting the output signalfed from the gray shade voltage generating circuit to, for example, 160(128+32), by inputting the least significant bit outputted from the datalatch circuit to the gray shade voltage selecting circuit and byproviding means for fixing 8-bit least significant bit to a low and highlevel based on digital image data.

The method for adjusting the voltage is not limited to the method inwhich the offset is produced for the voltage outputted from theoperational amplifier described above. For example, a C-DAC (SwitchedCapacitor—DA converter) method in which a switched capacitor is mountedbetween the gray shade selecting circuit and the operational amplifiermay be employed. In this case, the driving circuit may be so configuredthat only the resistance string method is employed depending on thedigital image data.

As described above, according to the present invention, since the numberof high order bits supplied to the gray shade voltage selecting circuitis smaller than that of the digital image data, the number of devicescan be reduced when compared with the case where all bits of the digitalimage data are supplied. Moreover, since the low order bit is fed to thevoltage adjusting means, the number of devices required is very small,thus enabling the chip area to be reduced and reducing the number oftimes of functional tests, resulting in cost reduction.

Furthermore, if the digital image data described above conforms topre-determined data, by employing the resistance string method, it ismade possible to display images having more proper shades of gray.

It is thus apparent that the present invention is not limited to theabove embodiments but may be changed and modified without departing fromthe scope and spirit of the invention.

Finally, the present application claims the priority of Japanese PatentApplication No. Hei11-037828 filed on Feb. 16, 1999, which is hereinincorporated by reference.

1. A driving circuit of a display device for displaying a plurality ofgray shades based on inputted digital image data comprising: gray shadevoltage generating means for generating a plurality of voltages; grayshade voltage selecting means for selecting one voltage out of aplurality of voltages supplied from said gray shade voltage generatingmeans based on high order bits composed of at least one bit counted fromthe most significant bit of said digital image data, and for outputtingsaid voltage; an operational amplifier used to amplify a voltageoutputted from said gray shade voltage selecting means; and voltageadjusting means for inducing a voltage rise or a voltage drop of avoltage outputted from said operational amplifier based on low orderbits of said digital image data.
 2. The driving circuit of the displaydevice according to claim 1, wherein said voltage adjusting means iscomprised of a resistor, one end of which is connected to an outputterminal of said operational amplifier, an active device connected toanother end of said resistor and controlling means for controllingoperations of said active device based on said low order bits of saiddigital image data, wherein said other end of said resistor is connectedto said display device.
 3. The driving circuit of the display deviceaccording to claim 1, wherein said active device has a first transistor,a drain of which is connected to said resistor, a source of which supplypower is applied to and a gate voltage of which is controlled by saidcontrolling means, and a second transistor a drain of which is connectedto said resistor, a source of which is connected to a ground and a gatevoltage of which is controlled by said controlling means.
 4. The drivingcircuit of the display device according to claim 1, wherein saidresistor is composed of an analog switch.
 5. The driving circuit of thedisplay device according to claim 1, wherein said gray shade voltagegenerating means is provided with two or more input terminals to whichan voltage is inputted from outside and with dividing means used todivide voltages inputted into said input terminals into many voltages.6. The driving circuit of the display device according to claim 1,wherein a voltage outputted from said gray shade voltage generatingmeans is a positive polarity voltage and a negative polarity voltage. 7.The driving circuit of the display device according to claim 1, wherein,when bits of said digital image data are N, said high order bits arecomposed of (N−1) bits counted from the most significant bit of saiddigital image data and the low order bit is composed of one bit countedfrom the least significant bit of the digital image data.
 8. A drivingcircuit of a display device for displaying a plurality of gray shadesbased on inputted digital image data comprising: a gray shade voltagegenerating circuit for generating a plurality of voltages; a gray shadevoltage selecting circuit for selecting one voltage out of a pluralityof voltages supplied from said gray shade voltage generating circuitbased on high order bits composed of at least one bit counted from themost significant bit of said digital image data, and for outputting saidvoltage; an operational amplifier used to amplify a voltage outputtedfrom said gray shade voltage selecting circuit; and a voltage adjustingcircuit for inducing a voltage rise or a voltage drop of a voltageoutputted from said operational amplifier based on low order bits ofsaid digital image data, wherein said voltage adjusting circuit iscomprised of a resistor, one end of which is connected to an outputterminal of said operational amplifier, an active device connected toanother end of said resistor and controlling circuit for controllingoperations of said active device based on said low order bits of saiddigital image data, wherein said other end of said resistor is connectedto said display device.
 9. The driving circuit of the display deviceaccording to claim 8, wherein said active device has a first transistor,a drain of which is connected to said another end of said resistor, asource of which supply power is applied to and a gate voltage of whichis controlled by said controlling circuit, and a second transistor adrain of which is connected to said another end of said resistor, asource of which is connected to a ground and a gate voltage of which iscontrolled by said controlling circuit.
 10. The driving circuit of thedisplay device according to claim 8, wherein said resistor is composedof an analog switch.
 11. The driving circuit of the display deviceaccording to claim 8, wherein a voltage outputted from said gray shadevoltage generating circuit is a positive polarity voltage and a negativepolarity voltage.
 12. The driving circuit of the display deviceaccording to claim 1, wherein, when bits of said digital image data areN, said high order bits are composed of (N−1) bits counted from the mostsignificant bit of said digital image data and the low order bit iscomposed of one bit counted from the least significant bit of thedigital image data.
 13. A driver for driving a display device inresponse to a plurality of input data, each of said input datacomprising a plurality of bits, said driving circuit comprising: a grayshade voltage generating circuit generating a plurality of gray shadevoltages, the number of said gray shade voltages being determined by thenumber of said bits of said input data, said gray shade voltages beingdivided into first and second groups of gray shade voltages, said firstgroup of gray shade voltages being generated by a resistance stringcircuit and said second group of gray shade voltages being generatedbased on at least two different ones of first group of gray shadevoltages; and a plurality of output terminals coupled to said displaydevice, each of said output terminal being provided for an associatedone of said input data and to supply said display device with one ofsaid gray shade voltages responsive to information of the associated oneof said input data.
 14. The driver as claimed in claim 13, wherein saidoutput terminal outputs one of said first group of gray shade voltageswhen said display device is driven with a first input data correspondingto a halftone region.
 15. The driver as claimed in claim 14, whereinsaid output terminal outputs one of said second group of gray shadevoltages when said display device is driven with a second input datacorresponding to said halftone region.
 16. The driver as claimed inclaim 15, wherein said output terminal outputs one of said first groupof gray shade voltages when said display device is driven with a thirdinput data corresponding to a non-halftone region.
 17. A driver fordriving a display device in response to a plurality of input data,comprising: a gray shade voltage generator for generating a plurality ofgray shade voltages; a gray shade voltage selector, selecting without avoltage up or a voltage drop, a first one of said gray shade voltageswhen said display is driven with a first input data corresponding to anon-halftone region, selecting without a voltage up or a voltage drop, asecond one of said gray shade voltages when said display is driven witha second input data corresponding to a halftone region, and selecting avoltage generated by a voltage up or a voltage drop of said second oneof said gray shade voltages when said display is driven with a thirdinput data corresponding to said halftone region; and an amplifieramplifying a voltage outputted from said gray shade voltage selector.18. The driver as claimed in claim 17, wherein said voltage generated bysaid voltage up or said voltage drop is generated by dividing accordingto said second one of said gray shade voltages and a voltage differentfrom said second one.